Intel Xeon Phi Road Map

Below we update when we know more about Intel's Xeon Phi. Please see our Xeon Phi page for more about use of the XPhi and how High End Compute provides support and access.

Xeon Phi Road Map

FLOPS/sec are quoted for double precision operations:

Model Knights Corner (KNC) Knights Landing (KNL) Knights Mill Knights Hill
Availability 2015 2016:
ninja (onboard KNL and no CPU) - now available
PCIe version likely to follow (presumably...)
2017 2017 (or later)
Processor Cores PCI-e

up to 61 cores

"up to 72" but appears to be shipping with 64 (Silvermont?) 1.3 GHz cores (supporting out-of-order execution); use of "tiles" (1 tile having 2 cores, sharing L2 cache, with tiles connected over a coherent mesh network)

14 nm

Memory connected to Micron's Hybrid Memory Cubes in-package, giving 16 GB "on-chip" MCDRAM memory. Choice of 3 boot-time MCDRAM configs: flat (MCDRAM and DRAM are separate), cache (MCDRAM is used by OS as fast cache for DRAM), hybrid (MCDRAM is part cache and part separate memory space)    
Manufacturing process 22 nm 14 nm   10 nm
Performance 1 TFLOPS/sec 3 TFLOPS/sec 24 TF/s of half-precision ie 16 bits (DP TF drops to 0.5 TF/s)
OS co-processor only co-processor or standalone that supports both Linux & MS Windows Server  
Misc   Supports Omni-Path off-chip communications;

Intel SDE for emulations

Targetted at AL/ML markets Omni-Path built-in